How does TCEX achieve a processing speed of 100,000 transactions per second?
Following the directives of Vietnam Resolution 05/2025/NQ-CP, Vietnam is undertaking a pilot project to operate a cryptocurrency exchange, and the technological capabilities of participating institutions have become a key factor of great interest. TCEX’s ability to process up to 100,000 transactions per second is considered a significant advancement in infrastructure development.
So, how does TCEX achieve this processing speed of 100,000 transactions per second?
Vietnam crypto exchange TCEX’s ability to achieve high throughput of 100,000 transactions per second (100k+ TPS) with ultra-low latency at the microsecond level essentially relies on a low-latency system architecture design that combines hardware and software. The core technical architecture and engineering optimizations are as follows:
1. In-Memory Matching Engine
Eliminating disk I/O bottlenecks: Traditional relational database-based architectures cannot meet the demands of 100,000 TPS. TCEX keeps the order book, account balances, and pending order status all resident in server memory (RAM).
High-speed data structure: Utilizing optimized red-black trees, skip lists, or doubly linked lists + hash tables, it achieves O(1) or O(log N) level fast lookup and matching of buy and sell orders under the price-time priority rule.
2. Single-threaded lock-free architecture and ring buffer (Lock-Free Ring Buffer / Disruptor)
Eliminating thread lock contention: Under high concurrency, thread contention for mutexes and context switches are major performance killers. The core matching logic of a single trading pair typically runs on a single thread, absolutely avoiding multi-threaded locking.
Memory lock-free queue (Disruptor mode): Between modules such as network reception, pre-risk control, matching, and market data broadcasting, a lock-free ring buffer is used for CPU cache-friendly event passing, greatly reducing CPU cache misses.
CPU Core Pinning: Binding the core matching process to a specific physical CPU core disables frequent CPU switching and ensures extremely high instruction cache hit rates.
3.Market/Symbol Sharding: Horizontal sharding and parallel computing by trading pair
Independent processing of a single asset: Individual trading pairs (such as BTC/USDT, ETH/USDT, or specific stocks/derivatives) must guarantee strict determination, therefore handled by independent single-threaded matching nodes.
Multi-Purpose Cluster Parallelism: The system distributes different trading pairs across different physical/logical node clusters. When dozens or hundreds of trading pairs run in parallel, the overall throughput can easily exceed 100,000 TPS.
4. Event Sourcing & Async Persistence
Decoupling pre-risk control from matching: Balance freezing and limit verification at order placement are completed in the memory preprocessing layer, without consuming CPU time slices of the core matching engine.
Asynchronous WAL Log Persistence: The matching engine is only responsible for quickly completing matching and generating transaction events in memory. The event stream is then asynchronously written to a memory buffer, and a separate background thread batch-flushes it to an NVMe SSD or a distributed message queue (such as Kafka), achieving “matching without waiting for disk.”
5. Kernel Bypass & Protocol Optimization
Network Layer Kernel Bypass: Employing technologies such as DPDK (Data Plane Development Kit) or Solarflare network interface cards (NICs), data packets are directly DMA-transferred from the NIC to user-space memory, bypassing the Linux kernel network stack and reducing memory copy and interrupt overhead.
Lightweight Binary Protocols: Abandoning bulky and slow-parsing JSON or XML, binary protocols such as Simple Binary Encoding (SBE), Protobuf, or FlatBuffers are used, significantly reducing serialization/deserialization latency.
6. Hardware and Low-Level Code Optimization
Memory Alignment and Cache Line Padding Elimination: In low-level languages like C++/Rust, core data structures are aligned to 64 bytes to prevent L1/L2 cache invalidation caused by modifications to adjacent variables by different CPU cores.
Branch Prediction and Inlining Optimization: Optimizing at the code level reduces branch missprediction, improving CPU pipeline execution efficiency.
However, while TCEX’s processing speed of 100,000 transactions per second is impressive, experts believe it’s not the decisive factor. In the cryptocurrency market, risk control capabilities and multi-layered security architectures are fundamental to protecting investors and ensuring secure operations.